学位論文

博士論文

2018

田口雄一

データ保護システムの性能評価およびサイジング方式の研究 PhD Thesis

情報システム学研究科情報ネットワークシステム学専攻, 2018.

Links | BibTeX

2017

中島拓真

動画配信サービスのための軽量分散協調キャッシュ基盤の研究 PhD Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2017.

Links | BibTeX

2015

Yasin Oge

Design and Evaluation of an FPGA-based Query Accelerator for Data Streams PhD Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2015.

Links | BibTeX

2013

CISSE AHMADOU DIT ADI

A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation PhD Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2013.

Links | BibTeX

2009

Masato Yoshimi

A Study on Monte-Carlo Biochemical Simulation for Field-Programmable Gate Arrays PhD Thesis

Keio University, 2009.

Abstract | Links | BibTeX

@phdthesis{dthesis09Yoshimi,

title = {A Study on Monte-Carlo Biochemical Simulation for Field-Programmable Gate Arrays},

author = {Masato Yoshimi},

url = {https://comp.lab.uec.ac.jp/wp-content/uploads/2013/08/yoshimi_phd_pub.pdf},

year = {2009},

date = {2009-03-23},

school = {Keio University},

abstract = {Since 1970s, many biologists and computer scientists have been studying various approach method- ologies to simulate chain chemical reactions inside living cells using computers. These studies were supported by rapid progress of computer performance and operational cost. Stochastic simulation method has become increasingly important for various study fields in the systems biology, which is a strategic research area that aims to analyze life processes as a system through simulations of biochemical models. Life processes often exhibit stochastic phenomena. Stochastic Biochemical Simulation Algorithm, which is abbreviated as SSA, is a method to calculate time changes of molec- ular numbers in a stochastic biochemical model. SSA requires vast number of repetitive computation, because it originates in a Monte-Carlo simulation methodology. Therefore, various algorithms have been developed to reduce the amount of calculation, and there are all many ongoing studies on the development of new computer system to achieve high-throughput.

Since 2000s, the baseline performance improvement procedure for microprocessor evolved from acceleration with high operational frequency to parallel operation using multi-core processor. Under such circumstance, a new type of computational systems is being focused for allocating a part of scientific operations to dedicated hardware in order to achieve both low-cost and high-performance. For example, Graphical Processing Units (GPUs) and other many-core processors in equipped in large-scale PC-clusters for the aim of reducing operational cost. Especially, a Field Programmable Gate Array is anticipated as an alternative for small- to middle-class PC-clusters with less than dozens of PCs, and various researches are now in progress. Dedicated systems with FPGAs allow high- speed or high-throughput computation by well-scheduled dataflow that fills up arithmetic pipelines solving the algorithm. However, just like other dedicated hardware, high-performance is achieved with FPGAs when algorithms have high loop-level parallelism, and conditional branches in the loop may degrade performance drastically. Performance improvement obtained by use of an FPGA greatly varies by the characteristics of target algorithm, because FPGAs have strict limitation of data size, dataflow and parallelism to achieve high throughput.

This work studies implementation and evaluation of two different SSAs on an FPGA, which aims to achieve high-performance compared to execution on microprocessors. The goal of this work is to clarify the relationship between algorithm, hardware architecture, and performance according to data size based on the evaluation results.

First SSA is called First Reaction Method (FRM). Processes in the algorithm is simple, and has high degree of loop- and data-level parallelism. Thus, the hardware design was fixed, and data flow was statically scheduled to enhance performance by consecutively injecting data into deep pipelines of floating point units. Arithmetic operations were configured faithfully to the original algorithm by single-precision floating-point data. We validated that the implemented hardware can treat small- scale models well. The design achieved more than 80-fold throughput compared to software execu- tion on Xeon 2.80 GHz, with large-scale biochemical systems for up to 1023 reactions.

Second SSA is called Next Reaction Method (NRM). The algorithm adopts two distinctive data structures: a binary tree in an Indexed Priority Que (IPQ) and a Dependency Graph (DG). They are used for improving computational efficiency over FRM for large-scale models, but processing time dynamically varies because of the nature of their data structures. Main concept of the design for executing NRM was to allow multi-thread execution. However, since it is highly difficult to achieve high throughput by naively exploiting data-level parallelism, the design adopted a data-driven methodology. The modules in implemented hardware are linked with an interconnection network. By modifying the network among modules, hardware design can be flexibly tuned to perform well on the target FPGA device. We found that the bus-based interconnection network achieves reasonable performance. It was evaluated with different number of threads, and through the result analysis we studied a methodology to reduce waiting time. The design achieved approximately 4.2 to 5.4 times higher throughput compared to execution on Core 2 Quad Q6600 2.40GHz.

And finally, the performance of two implementations for various size of biochemical model is discussed to lead to future development of scientific application using FPGAs.},

keywords = {},

pubstate = {published},

tppubtype = {phdthesis}

}

Since 1970s, many biologists and computer scientists have been studying various approach method- ologies to simulate chain chemical reactions inside living cells using computers. These studies were supported by rapid progress of computer performance and operational cost. Stochastic simulation method has become increasingly important for various study fields in the systems biology, which is a strategic research area that aims to analyze life processes as a system through simulations of biochemical models. Life processes often exhibit stochastic phenomena. Stochastic Biochemical Simulation Algorithm, which is abbreviated as SSA, is a method to calculate time changes of molec- ular numbers in a stochastic biochemical model. SSA requires vast number of repetitive computation, because it originates in a Monte-Carlo simulation methodology. Therefore, various algorithms have been developed to reduce the amount of calculation, and there are all many ongoing studies on the development of new computer system to achieve high-throughput.
Since 2000s, the baseline performance improvement procedure for microprocessor evolved from acceleration with high operational frequency to parallel operation using multi-core processor. Under such circumstance, a new type of computational systems is being focused for allocating a part of scientific operations to dedicated hardware in order to achieve both low-cost and high-performance. For example, Graphical Processing Units (GPUs) and other many-core processors in equipped in large-scale PC-clusters for the aim of reducing operational cost. Especially, a Field Programmable Gate Array is anticipated as an alternative for small- to middle-class PC-clusters with less than dozens of PCs, and various researches are now in progress. Dedicated systems with FPGAs allow high- speed or high-throughput computation by well-scheduled dataflow that fills up arithmetic pipelines solving the algorithm. However, just like other dedicated hardware, high-performance is achieved with FPGAs when algorithms have high loop-level parallelism, and conditional branches in the loop may degrade performance drastically. Performance improvement obtained by use of an FPGA greatly varies by the characteristics of target algorithm, because FPGAs have strict limitation of data size, dataflow and parallelism to achieve high throughput.
This work studies implementation and evaluation of two different SSAs on an FPGA, which aims to achieve high-performance compared to execution on microprocessors. The goal of this work is to clarify the relationship between algorithm, hardware architecture, and performance according to data size based on the evaluation results.
First SSA is called First Reaction Method (FRM). Processes in the algorithm is simple, and has high degree of loop- and data-level parallelism. Thus, the hardware design was fixed, and data flow was statically scheduled to enhance performance by consecutively injecting data into deep pipelines of floating point units. Arithmetic operations were configured faithfully to the original algorithm by single-precision floating-point data. We validated that the implemented hardware can treat small- scale models well. The design achieved more than 80-fold throughput compared to software execu- tion on Xeon 2.80 GHz, with large-scale biochemical systems for up to 1023 reactions.
Second SSA is called Next Reaction Method (NRM). The algorithm adopts two distinctive data structures: a binary tree in an Indexed Priority Que (IPQ) and a Dependency Graph (DG). They are used for improving computational efficiency over FRM for large-scale models, but processing time dynamically varies because of the nature of their data structures. Main concept of the design for executing NRM was to allow multi-thread execution. However, since it is highly difficult to achieve high throughput by naively exploiting data-level parallelism, the design adopted a data-driven methodology. The modules in implemented hardware are linked with an interconnection network. By modifying the network among modules, hardware design can be flexibly tuned to perform well on the target FPGA device. We found that the bus-based interconnection network achieves reasonable performance. It was evaluated with different number of threads, and through the result analysis we studied a methodology to reduce waiting time. The design achieved approximately 4.2 to 5.4 times higher throughput compared to execution on Core 2 Quad Q6600 2.40GHz.
And finally, the performance of two implementations for various size of biochemical model is discussed to lead to future development of scientific application using FPGAs.

修士論文

2019

岡田浩希

分散協調色キャッシュを用いた動画ライブ配信の効率化 Masters Thesis

情報理工学研究科情報・ネットワーク工学専攻, 2019.

Links | BibTeX

2018

千田進

動画配信網におけるアクセス変動予測を用いた分散協調キャッシュ制御 Masters Thesis

情報理工学研究科情報・ネットワーク工学専攻, 2018.

Links | BibTeX

2017

溝田敦也

インタークラウドを活用した遠隔データ保存の自動化機構 Masters Thesis

情報システム学研究科情報ネットワークシステム学専攻, 2017.

Links | BibTeX

多田昂介

マルチノードFPGAによるストリームデータ分散結合処理 Masters Thesis

情報システム学研究科情報ネットワークシステム学専攻, 2017.

Links | BibTeX

野島幸大

ネットワーク内キャッシュによる大規模ネットワーク通信電力の削減 Masters Thesis

情報システム学研究科情報ネットワークシステム学専攻, 2017.

Links | BibTeX

2015

城間隆行

複数キャッシュサーバの協調動作による高効率な動画配信基盤の構築 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2015.

BibTeX

土門憲司

RGB-Dセンサと機械学習による運転支援システム Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2015.

BibTeX

中井康介

配列類似性検索のFPGAを用いた並列計算 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2015.

Links | BibTeX

村田篤志

TSVを考慮した3次元積層プロセッサ向けフロアプランナの提案とマルチコアプロセッサの配置設計 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2015.

Links | BibTeX

野村隼人

長期再参照のためのキャッシュライン追い出し不可属性の提案 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2015.

Links | BibTeX

2014

工藤龍

複数FPGAボードを用いたビッグデータ分割処理に関する研究 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

Links | BibTeX

佐保田誠

プロセッサアーキテクチャ「STRAIGHT」のシミュレータ設計と評価 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

Links | BibTeX

椎野博文

Joinのためのデータ分割手法に関する研究 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

BibTeX

稲場朋大

配線アクティビティを考慮した3次元積層プロセッサ向けフロアプランナの提案とマルチコアプロセッサの配置設計 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

Links | BibTeX

岩崎央

See-Through Information Belt:光学シースルー方式HMDと直観的ジェスチャUIによるウェアラブルコンピューティングシステム Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

Links | BibTeX

山中崇弘

STRAIGHT アーキテクチャへのレジスタキャッシュ適用による電力削減効果 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

Links | BibTeX

千竃航平

ジェスチャUIと光学シースルーHMDによるハンズフリーマニュアルの提案 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

Links | BibTeX

力翠湖

プリフェッチ予測及び精度に基づく統合的キャッシュ管理手法 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

BibTeX

須戸里織

配列類似性検索のFPGAによる高速処理 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

BibTeX

伴大心

ネットワーク符号化機能を有するキャッシュを用いたコンテンツ配信法 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2014.

Links | BibTeX

2013

佐藤遼

カスタムプロセッサ構築用FPGAプラットフォームの開発と評価 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2013.

Links | BibTeX

重信裕政

包括的マッシュアップフレームワークIDUMOの拡張と評価 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2013.

Links | BibTeX

小野澤清人

自律ナビゲーションの実装による「浮遊ノート」システムの機能拡張とその応用 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2013.

Links | BibTeX

黒田修平

相対座標を用いた運動指導システムとその教本データの自動生成 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2013.

BibTeX

佐久間大輝

ウェアラブル心拍計を用いたストレス変動可視化による作業支援システムの研究 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2013.

BibTeX

中村勇勝

閾値秘密分散保持されたコンテンツの高信頼・高効率配信法 Masters Thesis

電気通信大学情報システム学研究科情報ネットワークシステム学専攻, 2013.

Links | BibTeX